<problem display_name="" graceperiod="0 day 5 hours 0 minutes 0 seconds" markdown="null" rerandomize="never" showanswer="always" start="2013-02-05T00:00" xqa_key="qaijS3UatK020Wc0sfCtFe0V6jpB4d64"> <startouttext/> <p>Many problems in real courses that use the schematic editor will have an initial position and question that you shold design a solution for. It will accept any of many correct solutions that solve its requirements.</p> <p> The following problem statement is contained within 6.002x: Circuits and Electronics.</p> <p>Design a circuit that implements a 3-input logic gate that implements \(Z = \lnot{(C(A+B))}\)</p> <p>Please add the appropriate pulldown network of mosfet switches connected to node Z to implement the truth table above, with \(R_{ON}\) of the mosfets chosen so that \(V_{ol}\) of the logic gate is less than \(0.25V\) for any combination of inputs. In the schematic tool, the mosfet model has \(V_{th} = 0.5V\), so \(V_{ol} \lt 0.25V\) will ensure that when the output of the logic gate is 0, if it is used as the input to some other logic gate, the mosfet to which it connects will be off.</p> <p> In the schematic tool, the mosfet model has \(R_n \approx 26.5k\Omega\) when using a \(3V\) power supply. To adjust \(R_{ON}\), double click the mosfet and select an appropriate value for the W/L parameter. For example, setting a mosfet's W/L to 10 would result in \(R_{ON} = 2.65k\Omega\).</p> <p>Note that the "Plot offset" property of the scope probes on the A, B and C signals has been set so that the plots will not overlap, making it easier to see what's happening.</p> <p>Please do not change the voltages of the voltage sources or the resistance of the pullup resistor.</p> <endouttext/> <schematicresponse> <center> <schematic height="500" width="600" parts="g,n,s" analyses="dc,tran" submit_analyses="{"tran":[["Z",0.0000004,0.0000009,0.0000014,0.0000019,0.0000024,0.0000029,0.0000034,0.000039]]}" initial_value="[["w",[112,96,128,96]],["w",[256,96,240,96]],["w",[192,96,240,96]],["s",[240,96,0],{"color":"cyan","offset":"","plot offset":"0","_json_":3},["Z"]],["w",[32,224,192,224]],["w",[96,48,192,48]],["L",[256,96,3],{"label":"Z","_json_":6},["Z"]],["r",[192,48,0],{"name":"Rpullup","r":"10K","_json_":7},["1","Z"]],["w",[32,144,32,192]],["w",[32,224,32,192]],["w",[48,192,32,192]],["w",[32,96,32,144]],["w",[48,144,32,144]],["w",[32,48,32,96]],["w",[48,96,32,96]],["w",[32,48,48,48]],["g",[32,224,0],{"_json_":16},["0"]],["v",[96,192,1],{"name":"VC","value":"square(3,0,250K)","_json_":17},["C","0"]],["v",[96,144,1],{"name":"VB","value":"square(3,0,500K)","_json_":18},["B","0"]],["v",[96,96,1],{"name":"VA","value":"square(3,0,1000K)","_json_":19},["A","0"]],["v",[96,48,1],{"name":"Vpwr","value":"dc(3)","_json_":20},["1","0"]],["L",[96,96,2],{"label":"A","_json_":21},["A"]],["w",[96,96,104,96]],["L",[96,144,2],{"label":"B","_json_":23},["B"]],["w",[96,144,104,144]],["L",[96,192,2],{"label":"C","_json_":25},["C"]],["w",[96,192,104,192]],["w",[192,96,192,112]],["s",[112,96,0],{"color":"red","offset":"15","plot offset":"0","_json_":28},["A"]],["w",[104,96,112,96]],["s",[112,144,0],{"color":"green","offset":"10","plot offset":"0","_json_":30},["B"]],["w",[104,144,112,144]],["w",[128,144,112,144]],["s",[112,192,0],{"color":"blue","offset":"5","plot offset":"0","_json_":33},["C"]],["w",[104,192,112,192]],["w",[128,192,112,192]],["view",0,0,2,"5","10","10MEG",null,"100","4us"]]"/> </center> <answer type="loncapa/python"> # for a schematic response, submission[i] is the json representation # of the diagram and analysis results for the i-th schematic tag def get_tran(json,signal): for element in json: if element[0] == 'transient': return element[1].get(signal,[]) return [] def get_value(at,output): for (t,v) in output: if at == t: return v return None output = get_tran(submission[0],'Z') okay = True # output should be 1, 1, 1, 1, 1, 0, 0, 0 if get_value(0.0000004,output) < 2.7: okay = False; if get_value(0.0000009,output) < 2.7: okay = False; if get_value(0.0000014,output) < 2.7: okay = False; if get_value(0.0000019,output) < 2.7: okay = False; if get_value(0.0000024,output) < 2.7: okay = False; if get_value(0.0000029,output) > 0.25: okay = False; if get_value(0.0000034,output) > 0.25: okay = False; if get_value(0.0000039,output) > 0.25: okay = False; correct = ['correct' if okay else 'incorrect'] </answer> </schematicresponse> <startouttext/> <p>When your circuit is ready for testing, run a \(4\mu s\) transient simulation to verify correct functionality and appropriate \(V_{ol}\) when the output of the gate is logic 0. To submit, please click CHECK. The checker will be verifying the voltage of the output node at several different times, so you'll earn a checkmark only <i>after</i> you've performed the transient simulation so that the checker will have a waveform to check!</p> <p>When the gate is correctly implemented, the plot produced by the transient analysis should like similar to the following figure.</p> <center><img src="/c4x/edX/DemoX/asset/images_logic_gate_image.png"/><br/>Figure 1. Example plot output </center> <p>Food for thought: You'll notice there are little spikes, sometimes called <i>glitches</i>, in the output waveform (see the bottom cyan-colored waveform in Figure 1). These only occur when the A and B inputs are changing simultaneously and the C input is high. Can you explain why? Think about what is happening in the pulldown circuitry at the time the glitches occur.</p> <endouttext/> <solution> <div class="detailed-solution"> <p>Explanation:</p> <p>We are asked to implement the logic function \( \overline{C\cdot\left(A + B\right)}\). This can be achieved with three transistors, as shown below; a series connection between \(C\) and \(\left(A+B\right)\) to implement the AND function, and a parallel connection between \(A\) and \(B\) to implement the OR function:</p> <img src="/c4x/edX/DemoX/asset/images_logic_gate_sln.png"/> <p>We are told that \(V_{DD} = 3V\) and that \(R_{n} = 26.5K\Omega\). Furthermore, we are told that we are to use the switch-resistor model of the MOSFETS, treating them like resistors with resistances \(R_{ON}\) when they are given a high input. \(R_{ON}\) has the form \(R_{ON} = 26.5K \cdot \frac{L}{W}\) . We need to determine \(R_{ON}\) by choosing the ratio \(\frac{L}{W}\) such that \(V_{OL}\) is always \(\lt 0.25V\).</p> <p>The first thing to do is to identify the scenario in which \(V_{OUT}\) takes on its maximum possible value in the context of a logical 0. This scenario corresponds to the worst-case \(V_{OL}\). There must be a full conducting path from \(V_{OUT}\) to ground to have a logical 0, which imposes the first condition. And because \(V_{OUT}\) is in the middle of a voltage divider between \(R_{pullup}\) and the equivalent "on" resistance of the MOS- FETs, we should be able to convince ourselves that \(V_{OL}\) takes on its highest value whenever the equivalent resistance of the "on" MOSFET network is the LARGEST because it is still constrained by an existing conducting path from \(V_{OUT}\) to ground.</p> <p>Finding the largest combination of resistances is simple: if we replace "on" transistors with resistors of resistance \(R_{ON}\), and "off" transistors with open circuits, we find the largest combination of resistance comes from a series connection between \(C\) and only one of \(A\) or \(B\), but NOT both. This results in an equivalent resistance of \(R_{EQ}=2\cdot R_{ON}\).</p> <p>We now solve for REQ using the voltage divider forumla: \[\frac{V_{DD}\cdot R_{EQ}}{R_{pullup} +R_{EQ}} \lt 0.25 \\ \] </p> <p>Plugging in for our values, we end up with \(R_{ON} \lt 454.56\) as our constraint. Plugging in once more into the given form of \(R_{ON}\), we end up with our final constraint on the transistor sizing: \[\frac{W}{L} \gt 58.3\\ \]</p> </div> </solution> </problem>